BibTeX record journals/jssc/LoLLLYCKLCCC19

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@article{DBLP:journals/jssc/LoLLLYCKLCCC19,
  author       = {Chieh{-}Pu Lo and
                  Wen{-}Zhang Lin and
                  Wei{-}Yu Lin and
                  Huan{-}Ting Lin and
                  Tzu{-}Hsien Yang and
                  Yen{-}Ning Chiang and
                  Ya{-}Chin King and
                  Chrong Jung Lin and
                  Yu{-}Der Chih and
                  Tsung{-}Yung Jonathon Chang and
                  Meng{-}Fan Chang},
  title        = {A ReRAM Macro Using Dynamic Trip-Point-Mismatch Sampling Current-Mode
                  Sense Amplifier and Low-DC Voltage-Mode Write-Termination Scheme Against
                  Resistance and Write-Delay Variation},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {54},
  number       = {2},
  pages        = {584--595},
  year         = {2019},
  url          = {https://doi.org/10.1109/JSSC.2018.2873588},
  doi          = {10.1109/JSSC.2018.2873588},
  timestamp    = {Thu, 14 Oct 2021 09:13:33 +0200},
  biburl       = {https://dblp.org/rec/journals/jssc/LoLLLYCKLCCC19.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}