BibTeX record journals/jssc/SinghKPVBN12

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@article{DBLP:journals/jssc/SinghKPVBN12,
  author       = {Vikas Singh and
                  Nagendra Krishnapura and
                  Shanthi Pavan and
                  Baradwaj Vigraham and
                  Debasish Behera and
                  Nimit Nigania},
  title        = {A 16 MHz {BW} 75 dB {DR} {CT} {\(\Delta\)}{\(\Sigma\)} {ADC} Compensated
                  for More Than One Cycle Excess Loop Delay},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {47},
  number       = {8},
  pages        = {1884--1895},
  year         = {2012},
  url          = {https://doi.org/10.1109/JSSC.2012.2196730},
  doi          = {10.1109/JSSC.2012.2196730},
  timestamp    = {Sun, 30 Aug 2020 00:13:24 +0200},
  biburl       = {https://dblp.org/rec/journals/jssc/SinghKPVBN12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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