BibTeX record journals/jssc/WangBHKNWZZB10

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@article{DBLP:journals/jssc/WangBHKNWZZB10,
  author       = {Yih Wang and
                  Uddalak Bhattacharya and
                  Fatih Hamzaoglu and
                  Pramod Kolar and
                  Yong{-}Gee Ng and
                  Liqiong Wei and
                  Ying Zhang and
                  Kevin Zhang and
                  Mark Bohr},
  title        = {A 4.0 GHz 291 Mb Voltage-Scalable {SRAM} Design in a 32 nm High-k
                  + Metal-Gate {CMOS} Technology With Integrated Power Management},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {45},
  number       = {1},
  pages        = {103--110},
  year         = {2010},
  url          = {https://doi.org/10.1109/JSSC.2009.2034082},
  doi          = {10.1109/JSSC.2009.2034082},
  timestamp    = {Thu, 14 Oct 2021 09:13:33 +0200},
  biburl       = {https://dblp.org/rec/journals/jssc/WangBHKNWZZB10.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}