BibTeX record journals/jssc/WangCLLW10

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@article{DBLP:journals/jssc/WangCLLW10,
  author       = {Jinn{-}Shyan Wang and
                  Chun{-}Yuan Cheng and
                  Je{-}Ching Liu and
                  Yu{-}Chia Liu and
                  Yi{-}Ming Wang},
  title        = {A Duty-Cycle-Distortion-Tolerant Half-Delay-Line Low-Power Fast-Lock-in
                  All-Digital Delay-Locked Loop},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {45},
  number       = {5},
  pages        = {1036--1047},
  year         = {2010},
  url          = {https://doi.org/10.1109/JSSC.2010.2047994},
  doi          = {10.1109/JSSC.2010.2047994},
  timestamp    = {Sun, 30 Aug 2020 00:12:37 +0200},
  biburl       = {https://dblp.org/rec/journals/jssc/WangCLLW10.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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