BibTeX record journals/tcas/NaKM17

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@article{DBLP:journals/tcas/NaKM17,
  author       = {Taesik Na and
                  Jong Hwan Ko and
                  Saibal Mukhopadhyay},
  title        = {Clock Data Compensation Aware Digital Circuits Design for Voltage
                  Margin Reduction},
  journal      = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
  volume       = {64-I},
  number       = {9},
  pages        = {2401--2413},
  year         = {2017},
  url          = {https://doi.org/10.1109/TCSI.2017.2695478},
  doi          = {10.1109/TCSI.2017.2695478},
  timestamp    = {Fri, 22 May 2020 13:28:14 +0200},
  biburl       = {https://dblp.org/rec/journals/tcas/NaKM17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

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