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"Hardness Analysis and Instrumentation of Verilog Gate Level Code for ..."

Abdul Rafay Khatri, Ali Hayek, Josef Börcsök (2017)

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DOI: 10.1007/978-3-319-56258-2_11

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-26

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Abdul Rafay Khatri, Ali Hayek, Josef Börcsök:
Hardness Analysis and Instrumentation of Verilog Gate Level Code for FPGA-based Designs. ARC 2017: 118-128

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