"FPGA acceleration of bit-true simulations for word-length optimization."

Javier Hormigo, Gabriel Caffarena (2021)

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DOI: 10.1109/ARITH51176.2021.00033

access: closed

type: Conference or Workshop Paper

metadata version: 2021-11-23

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Javier Hormigo, Gabriel Caffarena:
FPGA acceleration of bit-true simulations for word-length optimization. ARITH 2021: 119-122

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