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ORCID"Relaxed Simulated Tempering for VLSI Floorplan Designs."
Jason Cong et al. (1999)
- Jason Cong, Tianming Kong, Dongmin Xu, Faming Liang, Jun S. Liu, Wing Hung Wong:
Relaxed Simulated Tempering for VLSI Floorplan Designs. ASP-DAC 1999: 13-16
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