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ORCID"Fault simulation and test generation for clock delay faults."
Yoshinobu Higami et al. (2011)
- Yoshinobu Higami, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja:
Fault simulation and test generation for clock delay faults. ASP-DAC 2011: 799-805
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