"Design of a clock jitter reduction circuit using gated phase blending ..."

Kiichi Niitsu et al. (2013)

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DOI: 10.1109/ASPDAC.2013.6509577

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-21

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Kiichi Niitsu, Naohiro Harigai, Daiki Hirabayashi, Daiki Oki, Masato Sakurai, Osamu Kobayashi, Takahiro J. Yamaguchi, Haruo Kobayashi:
Design of a clock jitter reduction circuit using gated phase blending between self-delayed clock edges. ASP-DAC 2013: 103-104

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