"A reference-free on-chip timing jitter measurement circuit using ..."

Kiichi Niitsu et al. (2012)

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DOI: 10.1109/ASPDAC.2012.6165014

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-21

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Kiichi Niitsu, Masato Sakurai, Naohiro Harigai, Daiki Hirabayashi, Takahiro J. Yamaguchi, Haruo Kobayashi:
A reference-free on-chip timing jitter measurement circuit using self-referenced clock and a cascaded time difference amplifier in 65nm CMOS. ASP-DAC 2012: 553-554

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