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"A coherent hybrid SRAM and STT-RAM L1 cache architecture for shared memory ..."

Jianxing Wang et al. (2014)

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DOI: 10.1109/ASPDAC.2014.6742958

access: closed

type: Conference or Workshop Paper

metadata version: 2023-06-26

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Jianxing Wang, Yenni Tim, Weng-Fai Wong, Zhong-Liang Ong, Zhenyu Sun, Hai Li:
A coherent hybrid SRAM and STT-RAM L1 cache architecture for shared memory multicores. ASP-DAC 2014: 610-615

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