"Combined use of rising and falling edge triggered clocks for peak current ..."

Tsung-Yi Wu et al. (2010)

> Home

Details and statistics

DOI: 10.1109/ASPDAC.2010.5419842

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-26

- view
  authority control:
- export record
  dblp key:
  - conf/aspdac/WuKHLL10
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/aspdac/WuKHLL10
Tsung-Yi Wu, Tzi-Wei Kao, Shi-Yi Huang, Tai-Lun Li, How-Rern Lin:
Combined use of rising and falling edge triggered clocks for peak current reduction in IP-based SoC designs. ASP-DAC 2010: 444-449

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.