BibTeX record conf/asscc/FujiwaraCLWSWLC16

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@inproceedings{DBLP:conf/asscc/FujiwaraCLWSWLC16,
  author    = {Hidehiro Fujiwara and
               Yen{-}Huei Chen and
               Chih{-}Yu Lin and
               Wei{-}Cheng Wu and
               Dar Sun and
               Shin{-}Rung Wu and
               Hung{-}Jen Liao and
               Jonathan Chang},
  title     = {A 64-Kb 0.37V 28nm 10T-SRAM with mixed-Vth read-port and boosted {WL}
               scheme for IoT applications},
  booktitle = {{IEEE} Asian Solid-State Circuits Conference, {A-SSCC} 2016, Toyama,
               Japan, November 7-9, 2016},
  pages     = {185--188},
  publisher = {{IEEE}},
  year      = {2016},
  url       = {https://doi.org/10.1109/ASSCC.2016.7844166},
  doi       = {10.1109/ASSCC.2016.7844166},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/asscc/FujiwaraCLWSWLC16.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
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