BibTeX record conf/asscc/LiSCWTGJNISLCTV18

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@inproceedings{DBLP:conf/asscc/LiSCWTGJNISLCTV18,
  author    = {Shenggao Li and
               Fulvio Spagna and
               Ji Chen and
               Xiaoqing Wang and
               Luke Tong and
               Sujatha Gowder and
               Wenyan Jia and
               Roan Nicholson and
               Sitaraman Iyer and
               Rui Song and
               Lily Li and
               Meng{-}hung Chen and
               Amanda Tran and
               Michael De Vita and
               Deepar Govindrajan and
               Marcus Pasquarella and
               Dave Bradley and
               Frank Verdico and
               Matt Duwe and
               Eric Lee and
               Michelle Wigton},
  title     = {A Power and Area Efficient 2.5-16 Gbps Gen4 PCIe {PHY} in 10nm FinFET
               {CMOS}},
  booktitle = {{IEEE} Asian Solid-State Circuits Conference, {A-SSCC} 2018, Tainan,
               Taiwan, November 5-7, 2018},
  pages     = {5--8},
  year      = {2018},
  crossref  = {DBLP:conf/asscc/2018},
  url       = {https://doi.org/10.1109/ASSCC.2018.8579314},
  doi       = {10.1109/ASSCC.2018.8579314},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/asscc/LiSCWTGJNISLCTV18.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/asscc/2018,
  title     = {{IEEE} Asian Solid-State Circuits Conference, {A-SSCC} 2018, Tainan,
               Taiwan, November 5-7, 2018},
  publisher = {{IEEE}},
  year      = {2018},
  url       = {https://ieeexplore.ieee.org/xpl/conhome/8547238/proceeding},
  isbn      = {978-1-5386-6413-1},
  timestamp = {Sat, 10 Apr 2021 13:36:16 +0200},
  biburl    = {https://dblp.org/rec/conf/asscc/2018.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
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