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"VeriSketch: Synthesizing Secure Hardware Designs with Timing-Sensitive ..."

Armaiti Ardeshiricham et al. (2019)

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DOI: 10.1145/3319535.3354246

access: closed

type: Conference or Workshop Paper

metadata version: 2022-04-09

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  - conf/ccs/ArdeshirichamTG19
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Armaiti Ardeshiricham, Yoshiki Takashima, Sicun Gao, Ryan Kastner:
VeriSketch: Synthesizing Secure Hardware Designs with Timing-Sensitive Information Flow Properties. CCS 2019: 1623-1638

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