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"A 10-Gb/s CMOS clock and data recovery circuit using a secondary ..."

Woogeun Rhee et al. (2003)

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DOI: 10.1109/CICC.2003.1249364

access: closed

type: Conference or Workshop Paper

metadata version: 2021-11-15

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Woogeun Rhee, Herschel A. Ainspan, Sergey V. Rylov, Alexander V. Rylyakov, Michael P. Beakes, Daniel J. Friedman, Sudhir M. Gowda, Mehmet Soyuer:
A 10-Gb/s CMOS clock and data recovery circuit using a secondary delay-locked loop. CICC 2003: 81-84

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