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"A 90 nm FPGA I/O buffer design with 1.6 Gbps data rate for ..."
Jeffrey Tyhach et al. (2004)
- Jeffrey Tyhach, Bonnie Wang, Chiakang Sung, Joseph Huang, Khai Nguyen, Xiaobao Wang, Yan Chong, Philip Pan, Henry Kim, Gopinath Rangan, Tzung-Chin Chang, Johnson Tan:
A 90 nm FPGA I/O buffer design with 1.6 Gbps data rate for source-synchronous system and 300 MHz clock rate for external memory interface. CICC 2004: 431-434
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