"Architecture and methodology of a SoPC with 3.25Gbps CDR based SERDES and ..."

Ranianand Venkata et al. (2003)

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DOI: 10.1109/CICC.2003.1249481

access: closed

type: Conference or Workshop Paper

metadata version: 2021-11-15

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Ranianand Venkata, Wilson Wong, Tina Tran, Vinson Chan, Tim Hoang, Henry Lui, Uinh Ton, Sergey Shomurryev, Chong Lee, Shoujun Waiig, Huy Ngo, Malik Kdhani, Victor Maruri, Tin Lai, Tam Kpuyeu, Arch Zaliziiyak, Mei Luo, Toan Nguyen, Kazi Asaduzzaman, Siniardeep Maangat, John Lam, Rakesh Patel:
Architecture and methodology of a SoPC with 3.25Gbps CDR based SERDES and 1Gbps dynamic phase alignment. CICC 2003: 659-662

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