"A Systematic Technique for Verifying Critical Path Delays in a 300MHz ..."

Madhav P. Desai, Yao-Tsung Yen (1996)

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DOI: 10.1145/240518.240542

access: closed

type: Conference or Workshop Paper

metadata version: 2018-11-06

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Madhav P. Desai, Yao-Tsung Yen:
A Systematic Technique for Verifying Critical Path Delays in a 300MHz Alpha CPU Design Using Circuit Simulation. DAC 1996: 125-130

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