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"Proofs: A Fast, Memory Efficient Sequential Circuit Fault Simulator."

Thomas M. Niermann, Wu-Tung Cheng, Janak H. Patel (1990)

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DOI: 10.1145/123186.123396

access: closed

type: Conference or Workshop Paper

metadata version: 2018-11-06

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  - conf/dac/NiermannCP90
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Thomas M. Niermann, Wu-Tung Cheng, Janak H. Patel:
Proofs: A Fast, Memory Efficient Sequential Circuit Fault Simulator. DAC 1990: 535-540

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