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"Formal Verification of PowerPC Arrays Using Symbolic Trajectory Evaluation."

Manish Pandey et al. (1996)

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DOI: 10.1145/240518.240641

access: closed

type: Conference or Workshop Paper

metadata version: 2018-11-06

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  dblp key:
  - conf/dac/PandeyRBB96
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  - https://dblp.org/rec/conf/dac/PandeyRBB96
Manish Pandey, Richard Raimi, Derek L. Beatty, Randal E. Bryant:
Formal Verification of PowerPC Arrays Using Symbolic Trajectory Evaluation. DAC 1996: 649-654

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