"Verilog HDL, powered by PLI: a suitable framework for describing and ..."

Arash Saifhashemi, Hossein Pedram (2003)

> Home

Details and statistics

DOI: 10.1145/775832.775917

access: closed

type: Conference or Workshop Paper

metadata version: 2018-11-06

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/dac/SaifhashemiP03
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/dac/SaifhashemiP03
Arash Saifhashemi, Hossein Pedram:
Verilog HDL, powered by PLI: a suitable framework for describing and modeling asynchronous circuits at all levels of abstraction. DAC 2003: 330-333

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.