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"Optimal FPGA module placement with temporal precedence constraints."

Sándor P. Fekete, Ekkehard Köhler, Jürgen Teich (2001)

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DOI: 10.1109/DATE.2001.915093

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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  dblp key:
  - conf/date/FeketeKT01
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  persistent URL:
  - https://dblp.org/rec/conf/date/FeketeKT01
Sándor P. Fekete, Ekkehard Köhler, Jürgen Teich:
Optimal FPGA module placement with temporal precedence constraints. DATE 2001: 658-667

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