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"Detailed Placement for IR Drop Mitigation by Power Staple Insertion in ..."
Sun ik Heo et al. (2019)
- Sun ik Heo, Andrew B. Kahng, Minsoo Kim, Lutong Wang, Chutong Yang:
Detailed Placement for IR Drop Mitigation by Power Staple Insertion in Sub-10nm VLSI. DATE 2019: 830-835
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