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"Simulation Methodology for Analysis of Substrate Noise Impact on Analog / ..."
Charlotte Soens et al. (2005)
- Charlotte Soens, Geert Van der Plas, Piet Wambacq, Stéphane Donnay:
Simulation Methodology for Analysis of Substrate Noise Impact on Analog / RF Circuits Including Interconnect Resistance. DATE 2005: 270-275
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