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ORCID"Statistical Model for Logic Errors in CMOS Digital Circuits for ..."
Mohamed Abbas, Makoto Ikeda, Kunihiro Asada (2006)
- Mohamed Abbas, Makoto Ikeda, Kunihiro Asada:
Statistical Model for Logic Errors in CMOS Digital Circuits for Reliability-Driven Design Flow. DDECS 2006: 147-148
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