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"Exploiting High-Level Descriptions for Circuits Fault Tolerance Assessments."

Alfredo Benso et al. (1997)

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DOI: 10.1109/DFTVS.1997.628327

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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  dblp key:
  - conf/dft/BensoPRRRU97
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  persistent URL:
  - https://dblp.org/rec/conf/dft/BensoPRRRU97
Alfredo Benso, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Jaan Raik, Raimund Ubar:
Exploiting High-Level Descriptions for Circuits Fault Tolerance Assessments. DFT 1997: 212-217

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