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"Clock Synchronous Reset and Skew Calibration of 65GS/s ADCs in A ..."

Shankarram Athreya et al. (2018)

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DOI: 10.1109/ESSCIRC.2018.8494254

access: closed

type: Conference or Workshop Paper

metadata version: 2019-11-12

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  - conf/esscirc/AthreyaHKCVSZKW18
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Shankarram Athreya, Hiva Hedayati, Shayan Kazemkhani, Yanfei Chen, Saurabh Vats, Michael D. Scott, Bart Zeydel, Peter Keller, Jian Wang, Bhaskarareddy Avula, Boris Murmann, Echere Iroaga:
Clock Synchronous Reset and Skew Calibration of 65GS/s ADCs in A Multi-Lane Coherent Receiver. ESSCIRC 2018: 250-253

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