"A Method for Reducing Power Consumption of CMOS Logic Based on Signal ..."

J. Akita, K. Asada (1994)

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DOI: 10.1109/EDTC.1994.326842

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-24

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J. Akita, K. Asada:
A Method for Reducing Power Consumption of CMOS Logic Based on Signal Transition Probability. EDAC-ETC-EUROASIC 1994: 420-424

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