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"Rapid Cycle-Accurate Simulator for High-Level Synthesis."

Yuze Chi et al. (2019)

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DOI: 10.1145/3289602.3293918

access: closed

type: Conference or Workshop Paper

metadata version: 2020-08-05

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  dblp key:
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  - https://dblp.org/rec/conf/fpga/ChiCCW19
Yuze Chi, Young-kyu Choi, Jason Cong, Jie Wang:
Rapid Cycle-Accurate Simulator for High-Level Synthesis. FPGA 2019: 178-183

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