"Quality-Time Tradeoffs in Component-Specific Mapping: How to Train Your ..."

Hans Giesen et al. (2017)

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DOI: —

access: closed

type: Conference or Workshop Paper

metadata version: 2017-02-03

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  dblp key:
  - conf/fpga/GiesenRGD17
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  - https://dblp.org/rec/conf/fpga/GiesenRGD17
Hans Giesen, Raphael Rubin, Benjamin Gojman, André DeHon:
Quality-Time Tradeoffs in Component-Specific Mapping: How to Train Your Dynamically Reconfigurable Array of Gates with Outrageous Network-delays. FPGA 2017: 85-94

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