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"Multi-bit-width CNN Accelerator with Systolic-in-Systolic Dataflow and ..."

Mingqiang Huang et al. (2023)

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DOI: 10.1145/3543622.3573209

access: closed

type: Conference or Workshop Paper

metadata version: 2023-02-25

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  dblp key:
  - conf/fpga/HuangLHLW023
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  - https://dblp.org/rec/conf/fpga/HuangLHLW023
Mingqiang Huang, Yucen Liu, Sixiao Huang, Kai Li, Qiuping Wu, Hao Yu:
Multi-bit-width CNN Accelerator with Systolic-in-Systolic Dataflow and Single DSP Multiple Multiplication Scheme. FPGA 2023: 229

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