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"HiPR: Fast, Incremental Custom Partial Reconfiguration for HLS Developers."

Yuanlong Xiao, André DeHon (2022)

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DOI: 10.1145/3490422.3502335

access: closed

type: Conference or Workshop Paper

metadata version: 2022-02-14

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  dblp key:
  - conf/fpga/XiaoD22
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  - https://dblp.org/rec/conf/fpga/XiaoD22
Yuanlong Xiao, André DeHon:
HiPR: Fast, Incremental Custom Partial Reconfiguration for HLS Developers. FPGA 2022: 155

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