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"Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded ..."

Yifan Yang et al. (2019)

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DOI: 10.1145/3289602.3293902

access: closed

type: Conference or Workshop Paper

metadata version: 2023-09-30

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  dblp key:
  - conf/fpga/YangHWZ0GBLVWK19
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  - https://dblp.org/rec/conf/fpga/YangHWZ0GBLVWK19
Yifan Yang, Qijing Huang, Bichen Wu, Tianjun Zhang, Liang Ma, Giulio Gambardella, Michaela Blott, Luciano Lavagno, Kees A. Vissers, John Wawrzynek, Kurt Keutzer:
Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs. FPGA 2019: 23-32

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