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"Power Reduction for FPGA Implementations : Design Optimisation and High ..."

Shrutisagar Chandrasekaran, Abbes Amira (2006)

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DOI: 10.1109/FPL.2006.311363

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-21

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  - https://dblp.org/rec/conf/fpl/ChandrasekaranA06a
Shrutisagar Chandrasekaran, Abbes Amira:
Power Reduction for FPGA Implementations : Design Optimisation and High Level Modelling. FPL 2006: 1-2

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