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"Solving SAT with a Context-Switching Virtual Clause Pipeline and an FPGA ..."

Carlos J. Tavares et al. (2004)

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DOI: 10.1007/978-3-540-30117-2_36

access: closed

type: Conference or Workshop Paper

metadata version: 2023-06-09

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  - conf/fpl/TavaresBMS04
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Carlos J. Tavares, C. Bungardean, G. M. Matos, José T. de Sousa:
Solving SAT with a Context-Switching Virtual Clause Pipeline and an FPGA Embedded Processor. FPL 2004: 344-353

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