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ORCID"Using partial reconfiguration and high-level models to accelerate FPGA ..."
Yousef Iskander et al. (2010)
- Yousef Iskander, Stephen D. Craven, Athira Chandrasekharan, Sureshwar Rajagopalan, Guruprasad Subbarayan, Tannous Frangieh, Cameron D. Patterson:
Using partial reconfiguration and high-level models to accelerate FPGA design validation. FPT 2010: 341-344
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