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"Improved performance and yield with chip master planning design methodology."

Ali Jahanian, Morteza Saheb Zamani (2009)

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DOI: 10.1145/1531542.1531590

access: closed

type: Conference or Workshop Paper

metadata version: 2018-11-14

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  - https://dblp.org/rec/conf/glvlsi/JahanianZ09
Ali Jahanian, Morteza Saheb Zamani:
Improved performance and yield with chip master planning design methodology. ACM Great Lakes Symposium on VLSI 2009: 185-190

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