"Logic synthesis for low power using clock gating and rewiring."

Tak-Kei Lam et al. (2010)

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DOI: 10.1145/1785481.1785527

access: closed

type: Conference or Workshop Paper

metadata version: 2025-01-19

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Tak-Kei Lam, Steve Yang, Wai-Chung Tang, Yu-Liang Wu:
Logic synthesis for low power using clock gating and rewiring. ACM Great Lakes Symposium on VLSI 2010: 179-184

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