"Hardware-efficient propagate partial sad architecture for variable block ..."

Zhenyu Liu et al. (2007)

> Home

Details and statistics

DOI: 10.1145/1228784.1228826

access: closed

type: Conference or Workshop Paper

metadata version: 2020-11-23

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/glvlsi/LiuHSGI07
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/glvlsi/LiuHSGI07
Zhenyu Liu, Yiqing Huang, Yang Song, Satoshi Goto, Takeshi Ikenaga:
Hardware-efficient propagate partial sad architecture for variable block size motion estimation in H.264/AVC. ACM Great Lakes Symposium on VLSI 2007: 160-163

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.