Stop the war!

Остановите войну!

for scientists:

default search action

combined dblp search
author search
venue search
publication search

ask others

"FPGA Realization of Hardware-Flexible Parallel Structure FIR Filters Using ..."

Xuefeng Dai et al. (2020)

> Home

Details and statistics

DOI: 10.1109/I2MTC43012.2020.9129340

access: closed

type: Conference or Workshop Paper

metadata version: 2021-07-16

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/i2mtc/Dai0YZY20
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/i2mtc/Dai0YZY20
Xuefeng Dai, Jun Gu, Peng Ye, Yu Zhao, Kuojun Yang:
FPGA Realization of Hardware-Flexible Parallel Structure FIR Filters Using Combined Systolic Arrays. I2MTC 2020: 1-5

a service of

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.