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"Device-to-System Level Simulation Framework for STT-DMTJ Based Cache Memory."

Esteban Garzón et al. (2019)

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DOI: 10.1109/ICECS46596.2019.8965021

access: closed

type: Conference or Workshop Paper

metadata version: 2020-10-25

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  dblp key:
  - conf/icecsys/GarzonRCL19
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  - https://dblp.org/rec/conf/icecsys/GarzonRCL19
Esteban Garzón, Raffaele De Rose, Felice Crupi, Marco Lanuzza:
Device-to-System Level Simulation Framework for STT-DMTJ Based Cache Memory. ICECS 2019: 123-124

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