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"Parallel-pipelined architecture for 2-D ICT VLSI implementation."

Juan A. Michell, Gustavo A. Ruiz, Angel M. Burón (2003)

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DOI: 10.1109/ICIP.2003.1247188

access: closed

type: Conference or Workshop Paper

metadata version: 2019-02-18

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Juan A. Michell, Gustavo A. Ruiz, Angel M. Burón:
Parallel-pipelined architecture for 2-D ICT VLSI implementation. ICIP (3) 2003: 89-92

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