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"Designing soft-error-aware circuits with power and speed optimization."

H. Jiang et al. (2018)

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DOI: 10.1109/IRPS.2018.8353692

access: closed

type: Conference or Workshop Paper

metadata version: 2019-01-22

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  dblp key:
  - conf/irps/JiangZNMB18
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  - https://dblp.org/rec/conf/irps/JiangZNMB18
H. Jiang, H. Zhang, Balaji Narasimham, Lloyd W. Massengill, Bharat L. Bhuva:
Designing soft-error-aware circuits with power and speed optimization. IRPS 2018: 5-1

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