Stop the war!

Остановите войну!

for scientists:

default search action

combined dblp search
author search
venue search
publication search

ask others

"A 5-GHz fractional-N phase-locked loop with spur reduction technique in ..."

Wei-Hao Chiu, Chien-Yuan Cheng, Tsung-Hsien Lin (2010)

> Home

Details and statistics

DOI: 10.1109/ISCAS.2010.5538014

access: closed

type: Conference or Workshop Paper

metadata version: 2017-06-15

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/iscas/ChiuCL10
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/iscas/ChiuCL10
Wei-Hao Chiu, Chien-Yuan Cheng, Tsung-Hsien Lin:
A 5-GHz fractional-N phase-locked loop with spur reduction technique in 0.13-μm CMOS. ISCAS 2010: 2996-2999

a service of

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.