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"Energy-delay efficient asynchronous-logic 16×16-bit pipelined ..."

Weng-Geng Ho et al. (2012)

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DOI: 10.1109/ISCAS.2012.6272073

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-27

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Weng-Geng Ho, Kwen-Siong Chong, Tong Lin, Bah-Hwee Gwee, Joseph S. Chang:
Energy-delay efficient asynchronous-logic 16×16-bit pipelined multiplier based on Sense Amplifier-Based Pass Transistor Logic. ISCAS 2012: 492-495

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