"A 7.7mW/1.0ns/1.35V delay locked loop with racing mode and OA-DCC for DRAM ..."

Hyun-Woo Lee et al. (2010)

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DOI: 10.1109/ISCAS.2010.5537703

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-26

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Hyun-Woo Lee, Yong-Hoon Kim, Won-Joo Yun, Eun Young Park, Kang Youl Lee, Jaeil Kim, Kwang Hyun Kim, Jongho Jung, Kyung Whan Kim, Nam Gyu Rye, Kwan-Weon Kim, Jun Hyun Chun, Chulwoo Kim, Young-Jung Choi, Byong-Tae Chung, Joong Sik Kih:
A 7.7mW/1.0ns/1.35V delay locked loop with racing mode and OA-DCC for DRAM interface. ISCAS 2010: 3861-3864

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