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"An FPGA processor for real-time, fixed-point refinement of CDVS keypoints."

Giorgio Lopez et al. (2015)

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DOI: 10.1109/ISCAS.2015.7169276

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-26

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  - conf/iscas/LopezNMS15
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Giorgio Lopez, Ettore Napoli, Domenico Meglio, Antonio G. M. Strollo:
An FPGA processor for real-time, fixed-point refinement of CDVS keypoints. ISCAS 2015: 2832-2835

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