"An 8-bit 1.8 V 500 MS/s CMOS DAC with a novel four-stage current steering ..."

Santanu Sarkar et al. (2008)

> Home

Details and statistics

DOI: 10.1109/ISCAS.2008.4541376

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-26

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/iscas/SarkarPDBB08
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/iscas/SarkarPDBB08
Santanu Sarkar, Ravi Sankar Prasad, Sanjoy Kumar Dey, Vinay Belde, Swapna Banerjee:
An 8-bit 1.8 V 500 MS/s CMOS DAC with a novel four-stage current steering architecture. ISCAS 2008: 149-152

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.